Design of repairable and fully diagnosable folded PLAs for yield enhancement

Authors:
Chin-Long Wey;Jyhyeung Ding;Tsin-Yuan Chang
Affiliations:
Department of Electrical Engineering, Michigan State University, East Lansing, MI;Department of Electrical Engineering, Michigan State University, East Lansing, MI;Department of Electrical Engineering, National Tsing-Hua University, Hsin-Chu, Taiwan, Republic of China
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

The yield of ICs has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve the manufacturing and testing processes. This is very costly and quite difficult to implement. The practical approach is to use a fault-tolerant design. In this paper, a design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired with-out reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and has led to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.