A computer-aided-design system for segmented-folded PLA macro-cells
DAC '81 Proceedings of the 18th Design Automation Conference
Improving a PLA area by pull-up transistor folding
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Design of repairable and fully diagnosable folded PLAs for yield enhancement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On the equivalence of pull-up transistor assignment in PLA folding and distribution graph
SAC '94 Proceedings of the 1994 ACM symposium on Applied computing
APSS: An automatic PLA synthesis system
DAC '83 Proceedings of the 20th Design Automation Conference
Optimum reduction of programmable logic array
DAC '83 Proceedings of the 20th Design Automation Conference
A branch and bound algorithm for optimal pla folding
DAC '84 Proceedings of the 21st Design Automation Conference
Microassembly and area reduction techniques for PLA microcode
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Transformation from ad hoc EDA to algorithmic EDA
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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The notion of a bipartite folding of a PLA is introduced. An efficient branch and bound algorithm is presented which finds an optimal bipartite folding of a PLA. The experimental results give additional justification to this folding technique.