Introduction to VLSI Systems
Improving a PLA area by pull-up transistor folding
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
25 years of DAC Papers on Twenty-five years of electronic design automation
On the equivalence of pull-up transistor assignment in PLA folding and distribution graph
SAC '94 Proceedings of the 1994 ACM symposium on Applied computing
APSS: An automatic PLA synthesis system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
A branch and bound algorithm for optimal pla folding
DAC '84 Proceedings of the 21st Design Automation Conference
A depth-first branch-and-bound algorithm for optimal PLA folding
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal bipartite folding of PLA
DAC '82 Proceedings of the 19th Design Automation Conference
A layout synthesis system for NMOS gate-cells
DAC '82 Proceedings of the 19th Design Automation Conference
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A PLA structure incorporating segmenting and folding features intended for use as a macro-cell for VLSI applications is described. A brief outline of a computer-aided-design system for the layout synthesis of such PLAs is given. The objectives are the attainment of compact area, low design time, and ease of design Symbolic layout generation for the PLA is treated in detail and practical design algorithms for partitioning and folding are discussed. An example is used to illustrate currently achievable results.