The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A computer-aided-design system for segmented-folded PLA macro-cells
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Techniques for programmable logic array folding
DAC '82 Proceedings of the 19th Design Automation Conference
PAOLA: A tool for topological optimization of large PLAS
DAC '82 Proceedings of the 19th Design Automation Conference
A High Density Programmable Logic Array Chip
IEEE Transactions on Computers
Design of large ALUs using multiple PLA macros
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
An Algorithm for Optimal PLA Folding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Programmable logic arrays are important building blocks of VLSI circuits and systems. The problem of optimizing the silicon area and the performances of large logic arrays are addressed. In particular a general method is described for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. A constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs is defined. A new computer program, PLEASURE is presented. It implements several algorithms for multiple and/or constrained PLA folding.