Introduction to VLSI Systems
25 years of DAC Papers on Twenty-five years of electronic design automation
PLAYGROUND: minimization of PLAs with mixed ground true outputs
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
GENIE: a generalized array optimizer for VLSI synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Principles of the SYCO compiler
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Internal connection problem in large optimized PLAs
DAC '83 Proceedings of the 20th Design Automation Conference
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
Microassembly and area reduction techniques for PLA microcode
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
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This paper presents a tool, called PAOLA, for optimizing the layout of large PLAs used as decoders in VLSI systems. The optimization techniques it uses are heuristic. They involve compacting the AND/OR matrices by cutting and reorganizing the input/output lines in order to reduce the number of columns in these matrices. They also allow the lengthening of the shape of the PLA and the lateral access to the input/output segments. This eases the topological adaptation of different blocks in order to reduce the surface of the interconnection network between them. The layout of the PLA uses internal topological conflicts and ground refresh lines positions to improve accessibility to the input/output segments created inside the AND/OR matrices. This system has been tested on several examples including industrial PLAs. It gives an area reduction of the OR matrix of up to 50% on PLAs having 3000 to 5000 positions in the OR matrix with a computing time of 4 to 5 minutes on a main frame HB-68 computer running with the MULTICS operating system.