Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
PAOLA: A tool for topological optimization of large PLAS
DAC '82 Proceedings of the 19th Design Automation Conference
Computer-aided synthesis of pla-based systems
Computer-aided synthesis of pla-based systems
Automated synthesis of multi-level combinational logic in cmos technology
Automated synthesis of multi-level combinational logic in cmos technology
Array optimization for VLSI synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
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A new generalized array optimization scheme is presented which solves the problem of efficient automatic layout of multi-level CMOS and NMOS logic circuits. The new approach has been implemented in the program GENIE which can be used for the multiple folding of PLAS, as well as for compacting gate matrix layouts, SLAs, and Weinberger arrays. The cells in the array can be of non-uniform sizes and any form of constraint can be placed on the input and output terminals. The generalized array optimizer uses the combinatorial optimization technique called Simulated Annealing. Results obtained are uniformly better than existing specialized array optimizers and folding programs, particularly when the inputs locations are constrained. GENIE is the first program to produce high-quality, automated SLA implementations.