A fast maze router with iterative use of variable search space restriction
DAC '80 Proceedings of the 17th Design Automation Conference
PAOLA: A tool for topological optimization of large PLAS
DAC '82 Proceedings of the 19th Design Automation Conference
Dynamic Programming
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
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This paper describes a method to generate a path between any point of an “input segment” or an “output segment”, appearing inside a topological optimized PLA, and any point of the vicinity of the corresponding input or output terminal node, located on the periphery of the PLA. This method solves the internal routing problem by considering a number of obstacles constituted by the internal circuit elements (i.e. the transistors, ground lines, ground refresh lines, ...). The routing process is performed inside the PLA planes. Two kind of algorithms are presented. They respectively aim to solve the internal routing either in a double layer model, or in a single layer model. In both cases the shortest path is chosen, and the corresponding connection is placed by avoiding any violation of the design rules of the technology which is used.