Optimization of the PLA area

Authors:
J. F. Paillotin
Affiliations:
-
Venue:
DAC '81 Proceedings of the 18th Design Automation Conference
Year:
1981

Citing 1
Cited 7

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Computer-Aided Design

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Abstract

A method to reduce the area of the PLA's is presented. Two steps are considered: the permutation of the minterms (columns) and the compacting of the PLA. The method is illustrated on the NMOS technology.