MINI: a heuristic approach for logic minimization

Authors:
S. J. Hong;R. G. Cain;D. L. Ostapko
Affiliations:
IBM System Products Division laboratory in Poughkeepsie, New York;IBM System Development Division Laboratory, Poughkeepsie, New York;IBM System Products Division Laboratory, Poughkeepsie, New York
Venue:
IBM Journal of Research and Development
Year:
1974

Citing 4
Cited 18

Computer Reduction of Two-Level, Multiple-Output Switching Circuits

IEEE Transactions on Computers
A Method for the Fast Approximate Solution of Large Prime Implicant Charts

IEEE Transactions on Computers
A New Algorithm for Generating Prime Implicants

IEEE Transactions on Computers
Recursive Operators for Prime Implicant and Irredundant Normal Form Determination

IEEE Transactions on Computers

Lower Overhead Design for Testability of Programmable Logic Arrays

IEEE Transactions on Computers - The MIT Press scientific computation series
Heuristic Minimization of MVL Functions: A Direct Cover Approach

IEEE Transactions on Computers
Derivation of Minimal Sums for Completely Specified Functions

IEEE Transactions on Computers
Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs

IEEE Transactions on Computers
A New Approach to the Design of Testable PLA's

IEEE Transactions on Computers
Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs

IEEE Transactions on Computers
Knowledge discovery with second-order relations

Knowledge and Information Systems
Cubical CAMP for minimization of Boolean functions

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

IEEE Transactions on Computers
Input Variable Assignment and Output Phase Optimization of PLA's

IEEE Transactions on Computers
Redundancy and Don't Cares in Logic Synthesis

IEEE Transactions on Computers
A Method to Simplify a Boolean Function into a Near Minimal Sum-of-Products for Programmable Logic Arrays

IEEE Transactions on Computers
Pleasure: a computer program for simple/multiple constrained/unconstrained folding of programmable logic arrays

Computer-Aided Design
iCOACH: A circuit optimization aid for CMOS high-performance circuits

Integration, the VLSI Journal
Comprehensibility improvement of tabular knowledge bases

AAAI'93 Proceedings of the eleventh national conference on Artificial intelligence
Optimal logic synthesis and testability: two faces of the same coin

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Lower overhead design for testability of programmable logic arrays

ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Compact DSOP and Partial DSOP Forms

Theory of Computing Systems

Quantified Score

Hi-index	0.03

Visualization

Abstract

MINI is a heuristic logic minimization technique for many-variable problems. It accepts as input a Boolean logic specification expressed as an input-output table, thus avoiding a long list of minterms. It seeks a minimal implicant solution, without generating all prime implicants, which can be converted to prime implicants if desired. New and effective subprocesses, such as expanding, reshaping, and removing redundancy from cubes, are iterated until there is no further reduction in the solution. The process is general in that it can minimize both conventional logic and logic functions of multi-valued variables.