Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Logic Design and Switching Theory
Logic Design and Switching Theory
Logic Design of Digital Systems
Logic Design of Digital Systems
Digital Systems with Algorithm Implementation
Digital Systems with Algorithm Implementation
A State-Machine Synthesizer—SMS
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic PLA synthesis from a DDL-P description
DAC '81 Proceedings of the 18th Design Automation Conference
Interactive design language: A unified approach to hardware simulation, synthesis and documentation
DAC '82 Proceedings of the 19th Design Automation Conference
An Algebra for Logic Systems Switching Circuits Application
IEEE Transactions on Computers
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs
IEEE Transactions on Computers
On Input Permutation Technique for Multiple-Valued Logic Synthesis
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Decomposition of Multiple-Valued Functions
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Programmable logic circuits based on ambipolar CNFET
Proceedings of the 45th annual Design Automation Conference
Integration, the VLSI Journal
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Hi-index | 14.98 |
A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA's and PLA's with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.