Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
IEEE Transactions on Computers
Input Variable Assignment and Output Phase Optimization of PLA's
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
Logic Synthesis and Verification
Packet prediction for speculative cut-through switching
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
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Detecting essential primes is important in multiple-valued logic minimization. In this correspondence, we present a fast algorithm that can generate all essential primes without generating a prime cover of the Boolean function. A new consensus operation called asymmetric consensus (acons) is defined. In terms of acons, we prove a necessary and sufficient condition for detecting essential primes for a Boolean function with multiple-valued inputs. The detection of essential primes can be performed by using a tautology checking algorithm. We exploit the unateness of a Boolean function to speed up tautology checking. The notion of unateness considered is more general than that has appeared in the literature.