Automatic PLA synthesis from a DDL-P description

  • Authors:
  • S. Kang;W. M. vanCleemput

  • Affiliations:
  • -;-

  • Venue:
  • DAC '81 Proceedings of the 18th Design Automation Conference
  • Year:
  • 1981

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Abstract

This paper describes an automatic PLA synthesis (APLAS) system which automatically generates a PLA for the control function of a design from a DDL-P description of a digital system. APLAS can also minimize and partition the PLA to meet the design constraints. This is a very convenient tool for designing finite state machines. The control circuit of any digital system for which a state diagram can be drawn can be designed easily using this system.