Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Routing Table Compaction in Ternary CAM
IEEE Micro
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
A State-Machine Synthesizer—SMS
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic PLA synthesis from a DDL-P description
DAC '81 Proceedings of the 18th Design Automation Conference
Reducing TCAM Power Consumption and Increasing Throughput
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Algorithms for routing lookups and packet classification
Algorithms for routing lookups and packet classification
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
M-trie: an efficient approach to on-chip logic minimization
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
A memory- and time-efficient on-chip TCAM minimizer for IP lookup
Proceedings of the Conference on Design, Automation and Test in Europe
A resistive TCAM accelerator for data-intensive computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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Boolean logic minimization is being applied increasingly to a new variety of applications that demand very fast and frequent minimization services. These applications typically have access to very limited computing and memory resources, rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can execute with a data memory as little as 16 KB. We also found that the proposed approach can support up to 25 000 incremental updates per second. We also compare its performance for compaction of the routing access control list and demonstrate that the proposed approach is highly suitable for minimizing large access control lists containing several thousand entries. Therefore, the algorithm is ideal for on-chip logic minimization.