Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Introduction to Algorithms
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Routing Table Compaction in Ternary CAM
IEEE Micro
Proceedings of the 40th annual Design Automation Conference
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
IEEE Transactions on Computers
Fast incremental updates for pipelined forwarding engines
IEEE/ACM Transactions on Networking (TON)
Fast hash table lookup using extended bloom filter: an aid to network processing
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
Proceedings of the 33rd annual international symposium on Computer Architecture
An efficient approach to on-chip logic minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complexity of two-level logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ERID: edge router identification for fast forwarding packet in BGP domain
ICHIT'11 Proceedings of the 5th international conference on Convergence and hybrid information technology
Approaching optimal compression with fast update for large scale routing tables
Proceedings of the 2012 IEEE 20th International Workshop on Quality of Service
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Ternary content addressable memories (TCAMs) are becoming very popular due to the simple-to-design IP lookup units included in high-speed routers; they are fast and simple to manage, and they provide a one-clock lookup solution. However, a major drawback of TCAM-based IP lookup schemes lies in their high power consumption. Thus, the rapid increase of routing tables inevitably deteriorates TCAM power efficiency. Although on-chip TCAM minimizers aim for the TCAM power efficiency in a fast time and at a small memory amount, the minimizers are not efficient in a large scale prefix table. In this paper, we present a hash-based on-chip TCAM minimization for a power-and throughput-efficient IP lookup. In a hash-based TCAM minimization (HTM), we convert prefixes into keys and merge keys with a fast hash lookup in an O(nW) complexity, where n is the number of prefixes and W is the number of IP bits. Additionally, by building a forest of merging trees and choosing a subset among them, we can achieve a higher minimization ratio. The simulation with two routing tables shows that our HPM scheme uses 8.6 and 4.0 times fewer computation time and memory, compared to a contemporary on-chip minimizer.