Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
A Fast Algorithm for Optimum Height-Limited Alphabetic Binary Trees
SIAM Journal on Computing
Small forwarding tables for fast routing lookups
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
Scalable high speed IP routing lookups
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
PATRICIA—Practical Algorithm To Retrieve Information Coded in Alphanumeric
Journal of the ACM (JACM)
Memory-efficient state lookups with fast updates
Proceedings of the conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
Performance modeling for fast IP lookups
Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Fast Updating Algorithms for TCAMs
IEEE Micro
Routing Table Compaction in Ternary CAM
IEEE Micro
IP Address Lookup Made Fast and Simple
ESA '99 Proceedings of the 7th Annual European Symposium on Algorithms
Experimental Study of Internet Stability and Backbone Failures
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
IP-address lookup using LC-tries
IEEE Journal on Selected Areas in Communications
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
CAMP: fast and efficient IP lookup architecture
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Flashlook: 100-Gbps hash-tuned route lookup architecture
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Flashtrie: hash-based prefix-compressed trie for IP route lookup beyond 100Gbps
INFOCOM'10 Proceedings of the 29th conference on Information communications
A new IP lookup cache for high performance IP routers
Proceedings of the 47th Design Automation Conference
A memory- and time-efficient on-chip TCAM minimizer for IP lookup
Proceedings of the Conference on Design, Automation and Test in Europe
FlashTrie: beyond 100-Gb/s IP route lookup using hash-based prefix-compressed trie
IEEE/ACM Transactions on Networking (TON)
GAMT: a fast and scalable IP lookup engine for GPU-based software routers
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
A memory-efficient parallel routing lookup model with fast updates
Computer Communications
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Pipelined ASIC architectures are increasingly being used in forwarding engines for high-speed IP routers. We explore optimization issues in the design of memory-efficient data structures that support fast incremental updates in such forwarding engines. Our solution aims to balance the memory utilization across the multiple pipeline stages. We also propose a series of optimizations that minimize the disruption to the forwarding process caused by route updates. These optimizations reduce the update overheads by over a factor of two for a variety of different core routing tables and update traces.