Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
Fast Updating Algorithms for TCAMs
IEEE Micro
Longest prefix matching using bloom filters
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Efficient construction of multibit tries for IP lookup
IEEE/ACM Transactions on Networking (TON)
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Fast incremental updates for pipelined forwarding engines
IEEE/ACM Transactions on Networking (TON)
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
Non-random generator for IPv6 tables
HOTI '04 Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Efficient IP-address lookup with a shared forwarding table for multiple virtual routers
CoNEXT '08 Proceedings of the 2008 ACM CoNEXT Conference
Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines
Journal of Parallel and Distributed Computing
Building scalable virtual routers with trie braiding
INFOCOM'10 Proceedings of the 29th conference on Information communications
PacketShader: a GPU-accelerated software router
Proceedings of the ACM SIGCOMM 2010 conference
Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
A novel scalable IPv6 lookup scheme using compressed pipelined tries
NETWORKING'11 Proceedings of the 10th international IFIP TC 6 conference on Networking - Volume Part I
Hermes: an integrated CPU/GPU microarchitecture for IP routing
Proceedings of the 48th Design Automation Conference
SMALTA: practical and near-optimal FIB aggregation
Proceedings of the Seventh COnference on emerging Networking EXperiments and Technologies
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
A safe, efficient update protocol for openflow networks
Proceedings of the first workshop on Hot topics in software defined networks
Wire speed name lookup: a GPU-based approach
nsdi'13 Proceedings of the 10th USENIX conference on Networked Systems Design and Implementation
Compressing IP forwarding tables: towards entropy bounds and beyond
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM
Scalable IP lookups using shape graphs
ICNP '09 Proceedings of the 2009 17th IEEE International Conference on Network Protocols. ICNP 2009
GAMT: a fast and scalable IP lookup engine for GPU-based software routers
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Routing lookup, as a core function of routers for forwarding and filtering packets, has confronted with serious challenges nowadays, ranging from memory efficiency, update performance and throughput. Rather than seeking optimization techniques for the traditional lookup model, this paper presents a brand-new parallel lookup model, named Split Routing Lookup Model. In consideration of partial similarities among prefixes, we split all prefixes to produce redundancies, which are then removed during information integration. After that, the on-chip structure is compressed sharply. Besides, by such ''splitting'', route updates are diverged to be more targeted, and the lookup process is also decomposed to support parallel processing. With 14 real-world routing data, the proposed model is evaluated through 4 classic trie-based approaches, in comparison with their traditional implementations. The encouraging results show the superiorities of the proposed model in a comprehensive view. The on-chip memory savings are up to 99.2% and 94.8% for IPv4/6 respectively. While the reduction of update overhead, even in the worst case, is 50% and 30% respectively. Moreover, the pipeline depth is also reduced by 25-50%. Besides, another 2 techniques are selected to evaluate the proposed model on the virtual router platform. According to the results, based on the proposed model, 160KB on-chip memory is enough to store 14 virtual routers, each consuming only 11KB on average. In this way, the scalability of the proposed model to virtual routers is also clearly demonstrated.