Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Algorithm Design
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 2 - Volume 03
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
Survey and taxonomy of packet classification techniques
ACM Computing Surveys (CSUR)
Packet Forwarding Using Pipelined Multibit Tries
ISCC '06 Proceedings of the 11th IEEE Symposium on Computers and Communications
CAMP: fast and efficient IP lookup architecture
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Efficient Construction of Pipelined Multibit-Trie Router-Tables
IEEE Transactions on Computers
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Multi-terabit ip lookup using parallel bidirectional pipelines
Proceedings of the 5th conference on Computing frontiers
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
ERID: edge router identification for fast forwarding packet in BGP domain
ICHIT'11 Proceedings of the 5th international conference on Convergence and hybrid information technology
Scalable packet classification on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory-efficient parallel routing lookup model with fast updates
Computer Communications
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SRAM (static random access memory)-based pipelined algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high-throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines, as well as across different stages of each pipeline, must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order (i.e. the sequence) must be preserved. In this paper, we propose a parallel SRAM-based multi-pipeline architecture for IP lookup. A two-level mapping scheme is developed to balance the memory requirement among the pipelines as well as across the stages in each pipeline. To balance the traffic, we propose an early caching scheme to exploit the data locality inherent in the architecture. Our technique uses neither a large reorder buffer nor complex reorder logic. Instead, a flow-aware queuing scheme exploiting the flow information is used to maintain the intra-flow sequence. Extensive simulation using real-life traffic traces shows that the proposed architecture with 8 pipelines can achieve a throughput of up to 10 billion packets per second, i.e. 3.2 Tbps for minimum size (40 bytes) packets, while preserving intra-flow packet order.