Multi-terabit ip lookup using parallel bidirectional pipelines
Proceedings of the 5th conference on Computing frontiers
Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines
Journal of Parallel and Distributed Computing
Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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We propose a heuristic for the construction of variablestride multibit tries. These multibit tries are suitable for packet forwarding using a pipelined architecture. The variable-stride tries constructed by our heuristic require upto 1/32 of the per-stage memory required by optimal pipelined fixed-stride tries. We also develop a tree packing heuristic, which dramatically reduces the per-stage memory required by fixed- and variable-stride multibit tries constructed for pipelined architectures. On publicly available router databases, our tree packing heuristic reduces the maximum per-stage memory required by optimal pipelined fixed-stride tries