Scalable high speed IP routing lookups
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
Scalable high-speed prefix matching
ACM Transactions on Computer Systems (TOCS)
IP Lookup By Binary Search On Prefix Length
ISCC '03 Proceedings of the Eighth IEEE International Symposium on Computers and Communications
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
A B-Tree Dynamic Router-Table Design
IEEE Transactions on Computers
A novel reconfigurable hardware architecture for IP address lookup
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Shape Shifting Tries for Faster IP Route Lookup
ICNP '05 Proceedings of the 13TH IEEE International Conference on Network Protocols
Packet Forwarding Using Pipelined Multibit Tries
ISCC '06 Proceedings of the 11th IEEE Symposium on Computers and Communications
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
Non-random generator for IPv6 tables
HOTI '04 Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Towards 100G packet processing: Challenges and technologies
Bell Labs Technical Journal - Core and Wireless Networks
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
High throughput and large capacity pipelined dynamic search tree on FPGA
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Flashtrie: hash-based prefix-compressed trie for IP route lookup beyond 100Gbps
INFOCOM'10 Proceedings of the 29th conference on Information communications
High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
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High-speed IP lookup remains a challenging problem in next generation routers due to the ever increasing line rate and routing table size. In addition, the evolution towards IPv6 also requires long prefix length, sparse prefix distribution, and potentially very large routing tables. In this paper, we propose a novel Combined Length-Infix Pipelined Search (CLIPS) architecture for IPv6 routing table lookup on FPGA. CLIPS solves the longest prefix match (LPM) problem by combining both prefix length and infix pattern search. Binary search in prefix length is performed on the 64-bit routing prefix of IPv6 down to an 8-bit length range in log(64/8)=3 phases; each phase performs a fully-pipelined infix pattern search with only one external memory access. A fourth and the last phase then finds the LPM (if any) within the 8-bit length range in a compressed multi-bit trie. We describe the algorithms and data structures used for the CLIPS construction, run-time operation, dynamic update and false-positive avoidance. The proposed solution improves the on-chip memory efficiency on FPGA and maximizes the external SRAM utilization; additional properties for ensuring the practicality of our scheme include the modular construction, easy dynamic update, and simple resource allocation. Using a state-of-the-art FPGA, our CLIPS prototype supports up to 2.7 millioin IPv6 prefixes when employing 33 Mbits of BRAM and 4 channels of external SRAM. The prototype achieves a sustained throughput of 264 million IPv6 lookups per second, or 135 Gbps with minimum size (64-byte) packets.