Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Fast incremental updates for pipelined forwarding engines
IEEE/ACM Transactions on Networking (TON)
Fast hash table lookup using extended bloom filter: an aid to network processing
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Scalable, memory efficient, high-speed IP lookup algorithms
IEEE/ACM Transactions on Networking (TON)
Shape Shifting Tries for Faster IP Route Lookup
ICNP '05 Proceedings of the 13TH IEEE International Conference on Network Protocols
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
Proceedings of the 33rd annual international symposium on Computer Architecture
Longest prefix matching using bloom filters
IEEE/ACM Transactions on Networking (TON)
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
Non-random generator for IPv6 tables
HOTI '04 Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium
Multi-terabit ip lookup using parallel bidirectional pipelines
Proceedings of the 5th conference on Computing frontiers
Flashlook: 100-Gbps hash-tuned route lookup architecture
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
A novel scalable IPv6 lookup scheme using compressed pipelined tries
NETWORKING'11 Proceedings of the 10th international IFIP TC 6 conference on Networking - Volume Part I
Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Concise lookup tables for IPv4 and IPv6 longest prefix matching in scalable routers
IEEE/ACM Transactions on Networking (TON)
Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100- Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time updates to accommodate ever-growing routing tables. Some of the proposed multibit-trie based schemes, such as Tree Bitmap [1], have been used in today's high-end routers. However, their large data structure often requires multiple external memory accesses for each route lookup. A pipelining technique is widely used to achieve high-speed lookup with a cost of using many external memory chips. Pipelining also often leads to poor memory load-balancing. In this paper, we propose a new IP route lookup architecture called FlashTrie that overcomes the shortcomings of the multibit-trie based approach. We use a hash-based membership query to limit off-chip memory accesses per lookup to one and to balance memory utilization among the memory modules. We also develop a new data structure called Prefix-Compressed Trie that reduces the size of a bitmap by more than 80%. Our simulation and implementation results show that FlashTrie can achieve 160-Gbps worst-case throughput while simultaneously supporting 2-M prefixes for IPv4 and 279-k prefixes for IPv6 using one FPGA chip and four DDR3 SDRAM chips. FlashTrie also supports incremental real-time updates.