Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
Reflections on the memory wall
Proceedings of the 1st conference on Computing frontiers
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Algorithm Design
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting locality to ameliorate packet queue contention and serialization
Proceedings of the 3rd conference on Computing frontiers
Packet Forwarding Using Pipelined Multibit Tries
ISCC '06 Proceedings of the 11th IEEE Symposium on Computers and Communications
CAMP: fast and efficient IP lookup architecture
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Efficient Construction of Pipelined Multibit-Trie Router-Tables
IEEE Transactions on Computers
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Terabit switching: a survey of techniques and current products
Computer Communications
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines
Journal of Parallel and Distributed Computing
Flashlook: 100-Gbps hash-tuned route lookup architecture
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Flashtrie: hash-based prefix-compressed trie for IP route lookup beyond 100Gbps
INFOCOM'10 Proceedings of the 29th conference on Information communications
A novel scalable IPv6 lookup scheme using compressed pipelined tries
NETWORKING'11 Proceedings of the 10th international IFIP TC 6 conference on Networking - Volume Part I
FlashTrie: beyond 100-Gb/s IP route lookup using hash-based prefix-compressed trie
IEEE/ACM Transactions on Networking (TON)
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To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi-pipeline architecture for multi-terabit rate IP lookup. The architecture consists of multiple bidirectional linear pipelines, where each pipeline stores part of a routing table. We address the challenges of realizing such a solution. Two mapping schemes with different granularity are proposed to balance the memory distribution over different pipelines as well as across different stages in each pipeline. Also, IP caching is adopted to facilitate processing multiple packets per clock cycle. Instead of using large reorder buffers and complex logic, a lightweight scheduler and several small output delay queues are developed to preserve the intra-flow packet order. Simulation experiments using real-life data show that the proposed 4-pipeline architecture can store a core routing table with over 200K unique routing prefixes in less than 2 MB of memory, and can achieve a high throughput of up to 18.75 billion packets per second (GPPS), i.e. 6 Tbps for minimum size (40 bytes) packets.