Fast address lookups using controlled prefix expansion
ACM Transactions on Computer Systems (TOCS)
Memory-efficient state lookups with fast updates
Proceedings of the conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
The Power of Two Choices in Randomized Load Balancing
IEEE Transactions on Parallel and Distributed Systems
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Fast incremental updates for pipelined forwarding engines
IEEE/ACM Transactions on Networking (TON)
Fast hash table lookup using extended bloom filter: an aid to network processing
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Scalable, memory efficient, high-speed IP lookup algorithms
IEEE/ACM Transactions on Networking (TON)
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Shape Shifting Tries for Faster IP Route Lookup
ICNP '05 Proceedings of the 13TH IEEE International Conference on Network Protocols
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
Proceedings of the 33rd annual international symposium on Computer Architecture
CAMP: fast and efficient IP lookup architecture
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Longest prefix matching using bloom filters
IEEE/ACM Transactions on Networking (TON)
A TCAM-based distributed parallel IP lookup scheme and performance analysis
IEEE/ACM Transactions on Networking (TON)
Building high accuracy bloom filters using partitioned hashing
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Non-random generator for IPv6 tables
HOTI '04 Proceedings of the High Performance Interconnects, 2004. on Proceedings. 12th Annual IEEE Symposium
Multi-terabit ip lookup using parallel bidirectional pipelines
Proceedings of the 5th conference on Computing frontiers
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Flashlook: 100-Gbps hash-tuned route lookup architecture
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Progressive hashing for packet processing using set associative memory
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A novel IP-routing lookup scheme and hardware architecture for multigigabit switching routers
IEEE Journal on Selected Areas in Communications
A high-throughput and high-capacity IPv6 routing lookup system
Computer Networks: The International Journal of Computer and Telecommunications Networking
Compressing IP forwarding tables: towards entropy bounds and beyond
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks
Proceedings of the 50th Annual Design Automation Conference
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It is becoming apparent that the next-generation IP route lookup architecture needs to achieve speeds of 100 Gb/s and beyond while supporting IPv4 and IPv6 with fast real-time updates to accommodate ever-growing routing tables. Some of the proposed multibit-trie-based schemes, such as TreeBitmap, have been used in today's high-end routers. However, their large data structures often require multiple external memory accesses for each route lookup. A pipelining technique is widely used to achieve high-speed lookup with the cost of using many external memory chips. Pipelining also often leads to poor memory load-balancing. In this paper, we propose a new IP route lookup architecture called FlashTrie that overcomes the shortcomings of the multibit-trie-based approaches. We use a hash-based membership query to limit off-chip memory accesses per lookup and to balance memory utilization among the memory modules. By compacting the data structure size, the lookup depth of each level can be increased. We also develop a new data structure called Prefix-Compressed Trie that reduces the size of a bitmap by more than 80%. Our simulation and implementation results show that FlashTrie can achieve 80-Gb/s worst-case throughput while simultaneously supporting 2 M prefixes for IPv4 and 318 k prefixes for IPv6 with one lookup engine and two Double-Data-Rate (DDR3) SDRAM chips. When implementing five lookup engines on a state-of-the-art field programmable gate array (FPGA) chip and using 10 DDR3 memory chips, we expect FlashTrie to achieve 1-Gpps (packet per second) throughput, equivalent to 400 Gb/s for IPv4 and 600 Gb/s for IPv6. FlashTrie also supports incremental real-time updates.