Routing on longest-matching prefixes
IEEE/ACM Transactions on Networking (TON)
Operating systems (2nd ed.): design and implementation
Operating systems (2nd ed.): design and implementation
Scalable high speed IP routing lookups
SIGCOMM '97 Proceedings of the ACM SIGCOMM '97 conference on Applications, technologies, architectures, and protocols for computer communication
IP lookups using multiway and multicolumn search
IEEE/ACM Transactions on Networking (TON)
SF-LRU Cache Replacement Algorithm
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
V6Gene: A Scalable IPv6 Prefix Generator for Route Lookup Algorithm Benchmark
AINA '06 Proceedings of the 20th International Conference on Advanced Information Networking and Applications - Volume 01
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
IEEE Transactions on Computers
Fast binary and multiway prefix searches for packet forwarding
Computer Networks: The International Journal of Computer and Telecommunications Networking
A longest prefix first search tree for IP lookup
Computer Networks: The International Journal of Computer and Telecommunications Networking
Microprocessors & Microsystems
An efficient IP address lookup algorithm based on a small balanced tree using entry reduction
Computer Networks: The International Journal of Computer and Telecommunications Networking
Terabit switching: a survey of techniques and current products
Computer Communications
High-speed IP routing with binary decision diagrams based hardware address lookup engine
IEEE Journal on Selected Areas in Communications
FlashTrie: beyond 100-Gb/s IP route lookup using hash-based prefix-compressed trie
IEEE/ACM Transactions on Networking (TON)
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With the growing number of routing entries, IP routing lookup has become the major performance bottleneck in backbone routers. In this paper, a complete hardware-based routing lookup system is proposed to achieve high-throughput and high-capacity for IPv6. The proposed system is a cache-centric, hash-based architecture that contains a routing lookup application specific integrated circuit (ASIC) and a memory set. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The gate count of the ASIC, excluding the binary content addressable memory (BCAM), is about 5306 gates, using an in-house 0.18@mm CMOS single-poly six-metal standard cell library. The results of post-layout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100Gbps networks. The memory density is good, with each routing entry requiring only 64bits. Moreover, the routing table only needs 10.24KB on-chip BCAM, 20.04KB off-chip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.