The performance of cache-coherent ring-based multiprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
An approximate model of processor communication rings under heavy load
Information Processing Letters
Fast and scalable layer four switching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Memory-efficient state lookups with fast updates
Proceedings of the conference on Applications, Technologies, Architectures, and Protocols for Computer Communication
Scalable packet classification
Proceedings of the 2001 conference on Applications, technologies, architectures, and protocols for computer communications
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Performance Comparison of Hierarchical Ring- and Mesh- Connected Multiprocessor Networks
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
A pipelined memory architecture for high throughput network processors
Proceedings of the 30th annual international symposium on Computer architecture
The impact of address allocation and routing on the structure and implementation of routing tables
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Packet classification using multidimensional cutting
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Memory Hierarchy Design for a Multiprocessor Look-up Engine
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
CAMP: fast and efficient IP lookup architecture
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Virtually Pipelined Network Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Multi-terabit ip lookup using parallel bidirectional pipelines
Proceedings of the 5th conference on Computing frontiers
Large-scale wire-speed packet classification on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines
Journal of Parallel and Distributed Computing
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
High-bandwidth network memory system through virtual pipelines
IEEE/ACM Transactions on Networking (TON)
Reducing dynamic power dissipation in pipelined forwarding engines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Energy-efficient multi-pipeline architecture for terabit packet classification
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Design and implementation of the PLUG architecture for programmable and efficient network lookups
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Array design for trie-based IP lookup
IEEE Communications Letters
Range Tries for scalable address lookup
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Progressive hashing for packet processing using set associative memory
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Advanced hashing schemes for packet forwarding using set associative memory architectures
Journal of Parallel and Distributed Computing
A novel scalable IPv6 lookup scheme using compressed pipelined tries
NETWORKING'11 Proceedings of the 10th international IFIP TC 6 conference on Networking - Volume Part I
Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
LEAP: latency- energy- and area-optimized lookup pipeline
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
An architecture for IPv6 lookup using parallel index generation units
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Scalable packet classification on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SWSL: software synthesis for network lookup
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this results in unevenly distributed memory. To address this imbalance, conventional approaches use either complex dynamic memory allocation schemes or over-provision each of the pipeline stages. This paper describes the microarchitecture of a novel network search processor which provides both high execution throughput and balanced memory distribution by dividing the tree into subtrees and allocating each subtree separately, allowing searches to begin at any pipeline stage. The architecture is validated by implementing and simulating state of the art solutions for IPv4 lookup, VPN forwarding and packet classification. The new pipeline scheme and memory allocator can provide searches with a memory allocation efficiency that is within 1% of non-pipelined schemes.