LEAP: latency- energy- and area-optimized lookup pipeline

Authors:
Eric N. Harris;Samuel L. Wasmundt;Lorenzo De Carli;Karthikeyan Sankaralingam;Cristian Estan
Affiliations:
University of Wisconsin-Madison, Madison, WI, USA;University of Wisconsin-Madison, Madison, WI, USA;University of Wisconsin-Madison, Madison, WI, USA;University of Wisconsin-Madison, Madison, WI, USA;Broadcom, Irvine, CA, USA
Venue:
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Year:
2012

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Abstract

Table lookups and other types of packet processing require so much memory bandwidth that the networking industry has long been a major consumer of specialized memories like TCAMs. Extensive research in algorithms for longest prefix matching and packet classification has laid the foundation for lookup engines relying on area- and power-efficient random access memories. Motivated by costs and semiconductor technology trends, designs from industry and academia implement multi-algorithm lookup pipelines by synthesizing multiple functions into hardware, or by adding programmability. In existing proposals, programmability comes with significant overhead. We build on recent innovations in computer architecture that demonstrate the efficiency and flexibility of dynamically synthesized accelerators. In this paper we propose LEAP, a latency- energy- and area- optimized lookup pipeline based on an analysis of various lookup algorithms. We compare to PLUG, which relies on von-Neumann-style programmable processing. We show that LEAP has equivalent flexibility by porting all lookup algorithms previously shown to work with PLUG. At the same time, LEAP reduces chip area by 1.5X, power consumption by 1.3X, and latency typically by 5X. Furthermore, programming LEAP is straight-forward; we demonstrate an intuitive Python-based API.