Energy-efficient signal processing using FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Packet classification using multidimensional cutting
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Efficient packet classification for network intrusion detection using FPGA
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Algorithm Design
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
Algorithms for advanced packet classification with ternary CAMs
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Survey and taxonomy of packet classification techniques
ACM Computing Surveys (CSUR)
DPPC-RE: TCAM-Based Distributed Parallel Packet Classification with Range Encoding
IEEE Transactions on Computers
Fast packet classification using bloom filters
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Low power architecture for high speed packet classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A Memory-Efficient FPGA-based Classification Engine
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Large-scale wire-speed packet classification on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
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Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high throughput, they are not scalable with respect to power consumption. On the other hand, mapping decision-tree-based packet classification algorithms onto SRAM-based pipeline architectures becomes a promising alternative to TCAMs. However, existing SRAM-based algorithmic solutions need a variable number of accesses to large memories to classify a packet, and thus suffer from high energy dissipation in the worst case. This paper proposes a partitioning-based multi-pipeline architecture for energy-efficient packet classification. We optimize the HyperCuts algorithm, which is considered among the most scalable packet classification algorithms, and build a decision tree with a bounded height. Then we study two different schemes to partition the decision tree into several disjoint subtrees and map them onto multiple SRAM-based pipelines. Only one pipeline is active for classifying each packet, which takes a bounded number of accesses to small memories. Thus the energy dissipation is reduced. Simulation experiments using both real-life and synthetic traces show that the proposed architecture with 8 pipelines can store up to 10K unique rules in 0.336 MB SRAM, sustains 1 Tbps throughput, and achieves 2.25-fold reduction in energy dissipation over the baseline pipeline architecture that is not partitioned.