ClassBench: a framework for automated class testing
Software—Practice & Experience
Packet classification using tuple space search
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification using multidimensional cutting
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Packet Classification Using Extended TCAMs
ICNP '03 Proceedings of the 11th IEEE International Conference on Network Protocols
Scalable packet classification
IEEE/ACM Transactions on Networking (TON)
DPPC-RE: TCAM-Based Distributed Parallel Packet Classification with Range Encoding
IEEE Transactions on Computers
Conserving network processor power consumption by exploiting traffic variability
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable Packet Classification for Enabling Internet Differentiated Services
IEEE Transactions on Multimedia
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
Large-scale wire-speed packet classification on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
LOP: a novel SRAM-based architecture for low power and high throughput packet classification
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reducing dynamic power dissipation in pipelined forwarding engines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Energy-efficient multi-pipeline architecture for terabit packet classification
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
An energy-efficient FPGA-based packet processing framework
EUNICE'10 Proceedings of the 16th EUNICE/IFIP WG 6.6 conference on Networked services and applications: engineering, control and management
An FPGA-based fast classifier with high generalization property
ACM SIGARCH Computer Architecture News
Power-Aware Parallel Forwarding: An Optimization Study
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
400 Gb/s Programmable Packet Parsing on a Single FPGA
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Speedy FPGA-based packet classifiers with low on-chip memory requirements
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Scalable packet classification on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware accelerators targeting a novel group based packet classification algorithm
International Journal of Reconfigurable Computing
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Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Internet traffic. With everincreasing ruleset size and line speed, the task of implementing wire speed packet classification with reduced power consumption remains difficult. Software approaches are unable to classify packets at wire speed as line rates reach OC-768, while state of the art hardware approaches such as TCAM still consume large amounts of power. This paper presents a low power architecture for a high speed packet classifier which can meet OC-768 line rate. The architecture consists of an adaptive clocking unit which dynamically changes the clock speed of an energy efficient packet classifier to match fluctuations in traffic on a router line card. It achieves this with the help of a scheme developed to keep clock frequencies at the lowest speed capable of servicing the line card while reducing frequency switches. The low power architecture has been tested on OC-48, OC-192 and OC-768 packet traces created from real life network traces obtained from NLANR while classifying packets using synthetic rulesets containing up to 25,000 rules. Simulation results of our classifier implemented on a Cyclone 3 and Stratix 3 FPGA, and as an ASIC show that power savings of between 17--88% can be achieved, using our adaptive clocking unit rather than a fixed clock speed.