High-speed policy-based packet forwarding using efficient multi-dimensional range matching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification using multidimensional cutting
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Tree bitmap: hardware/software IP lookups with incremental updates
ACM SIGCOMM Computer Communication Review
Efficient packet classification for network intrusion detection using FPGA
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Tree Based Router Search Engine Architecture with Single Port Memories
Proceedings of the 32nd annual international symposium on Computer Architecture
Algorithms for advanced packet classification with ternary CAMs
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Survey and taxonomy of packet classification techniques
ACM Computing Surveys (CSUR)
Fast packet classification using bloom filters
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
ClassBench: a packet classification benchmark
IEEE/ACM Transactions on Networking (TON)
Two stage packet classification using most specific filter matching and transport level sharing
Computer Networks: The International Journal of Computer and Telecommunications Networking
OpenFlow: enabling innovation in campus networks
ACM SIGCOMM Computer Communication Review
Implementing an OpenFlow switch on the NetFPGA platform
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Acceleration of decision tree searching for IP traffic classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Low power architecture for high speed packet classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A Memory-Efficient FPGA-based Classification Engine
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
A Scalable High Throughput Firewall in FPGA
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Large-scale wire-speed packet classification on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines
Journal of Parallel and Distributed Computing
Accelerating OpenFlow switching with network processors
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A Power and Throughput-Efficient Packet Classifier with n Bloom Filters
IEEE Transactions on Computers
Algorithms for packet classification
IEEE Network: The Magazine of Global Internetworking
Optimal packet classification applicable tothe OpenFlow context
Proceedings of the first edition workshop on High performance and programmable networking
Hardware accelerators targeting a novel group based packet classification algorithm
International Journal of Reconfigurable Computing
Scalable ternary content addressable memory implementation using FPGAs
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
High-performance architecture for dynamically updatable packet classification on FPGA
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
An impulse-c hardware accelerator for packet classification based on fine/coarse grain optimization
International Journal of Reconfigurable Computing
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Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It has become a great challenge to develop scalable solutions for next-generation packet classification that support higher throughput, larger rule sets and more packet header fields. This paper exploits the abundant parallelism and other desirable features provided by current field-programmable gate arrays (FPGAs), and proposes a decision-tree-based, 2-D multi-pipeline architecture for next-generation packet classification. We revisit the techniques for traditional 5-tuple packet classification and propose several optimization techniques for the state-of-the-art decision-tree-based algorithm. Given a set of 12-tuple rules, we develop a framework to partition the rule set into multiple subsets each of which is built into an optimized decision tree. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization while sustaining high throughput. The implementation results show that our architecture can store either 10K real-life 5-tuple rules or 1K synthetic 12-tuple rules in on-chip memory of a single state-of-the-art FPGA, and sustain 80 and 40 Gbps throughput for minimum size (40 bytes) packets, respectively.