High-speed policy-based packet forwarding using efficient multi-dimensional range matching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification using tuple space search
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification using multidimensional cutting
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Scalable packet classification
IEEE/ACM Transactions on Networking (TON)
Survey and taxonomy of packet classification techniques
ACM Computing Surveys (CSUR)
Practical fpga programming in c
Practical fpga programming in c
Low power architecture for high speed packet classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A Memory-Efficient FPGA-based Classification Engine
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
A Scalable High Throughput Firewall in FPGA
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Hierarchical packet classification using a Bloom filter and rule-priority tries
Computer Communications
A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Packet classification as a fundamental network primitive
Packet classification as a fundamental network primitive
Topological transformation approaches to TCAM-based packet classification
IEEE/ACM Transactions on Networking (TON)
International Journal of Reconfigurable Computing
Scalable packet classification on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An impulse-c hardware accelerator for packet classification based on fine/coarse grain optimization
International Journal of Reconfigurable Computing
| Hi-index | 0.00 |
Packet classification is a ubiquitous and key building block formany critical network devices.However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 Megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on a Xeon processor operating at 3.4GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP) implementation, and two pure Register-Transfer Level (RTL) implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on a Xeon processor.