PCIU: hardware implementations of an efficient packet classification algorithm with an incremental update capability

Authors:
O. Ahmed;S. Areibi;K. Chattha;B. Kelly
Affiliations:
School of Engineering, University of Guelph, Guelph, ON, Canada;School of Engineering, University of Guelph, Guelph, ON, Canada;School of Engineering, University of Guelph, Guelph, ON, Canada;School of Engineering, University of Guelph, Guelph, ON, Canada
Venue:
International Journal of Reconfigurable Computing
Year:
2011

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Abstract

Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.