Packet Classification Using Extended TCAMs
ICNP '03 Proceedings of the 11th IEEE International Conference on Network Protocols
Survey and taxonomy of packet classification techniques
ACM Computing Surveys (CSUR)
Reconfigurable hardware for high-security/high-performance embedded systems: the SAFES perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient regular expression evaluation: theory to practice
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Field-split parallel architecture for high performance multi-match packet classification using FPGAs
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Efficient multi-ported memories for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
400 Gb/s Programmable Packet Parsing on a Single FPGA
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
FPGA Implementation of SRAM-based Ternary Content Addressable Memory
IPDPSW '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN
Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM
Scalable packet classification on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exact Worst Case TCAM Rule Expansion
IEEE Transactions on Computers
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Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.