ACM Transactions on Computer Systems (TOCS)
Network Systems Design Using Network Processors
Network Systems Design Using Network Processors
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Algorithms for advanced packet classification with ternary CAMs
Proceedings of the 2005 conference on Applications, technologies, architectures, and protocols for computer communications
Overcoming the memory wall in packet processing: hammers or ladders?
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
Compiling PCRE to FPGA for accelerating SNORT IDS
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
High-speed packet classification using binary search on length
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Implementing an OpenFlow switch on the NetFPGA platform
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Low power architecture for high speed packet classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Packet header analysis and field extraction for multigigabit networks
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
packetC Language for High Performance Packet Processing
HPCC '09 Proceedings of the 2009 11th IEEE International Conference on High Performance Computing and Communications
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
High throughput and large capacity pipelined dynamic search tree on FPGA
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
A Comparative Study on the Architecture Templates for Dynamic Nested Loops
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Leaping multiple headers in a single bound: wire-speed parsing using the kangaroo system
INFOCOM'10 Proceedings of the 29th conference on Information communications
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
Proceedings of the ACM SIGCOMM 2010 conference
EffiCuts: optimizing packet classification for memory and throughput
Proceedings of the ACM SIGCOMM 2010 conference
A folded pipeline network processor architecture for 100 Gbit/s networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Chimpp: a click-based programming and simulation environment for reconfigurable networking hardware
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Simplifying data path processing in next-generation routers
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
High throughput architecture for packet classification using FPGA
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Range Tries for scalable address lookup
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Low-latency modular packet header parser for FPGA
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
From 1G to 10G: code reuse in action
Proceedings of the first edition workshop on High performance and programmable networking
A comprehensive performance analysis of virtual routers on FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Design principles for packet parsers
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
Scalable ternary content addressable memory implementation using FPGAs
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Packet parsing is necessary at all points in the modern networking infrastructure, to support packet classification and security functions, as well as for protocol implementation. Increasingly high line rates call for advanced hardware packet processing solutions, while increasing rates of change call for high-level programmability of these solutions. This paper presents an approach for harnessing modern Field Programmable Gate Array (FPGA) devices, which are a natural technology for implementing the necessary high-speed programmable packet processing. The paper introduces PP: a simple high-level language for describing packet parsing algorithms in an implementation-independent manner. It demonstrates that this language can be compiled to give high-speed FPGA-based packet parsers that can be integrated alongside other packet processing components to build network nodes. Compilation involves generating virtual processing architectures tailored to specific packet parsing requirements. Scalability of these architectures allows parsing at line rates from 1 to 400 Gb/s as required in different network contexts. Run-time programmability of these architectures allows dynamic updating of parsing algorithms during operation in the field. Implementation results show that programmable packet parsing of 600 million small packets per second can be supported on a single Xilinx Virtex-7 FPGA device handling a 400 Gb/s line rate.