Fast Approximate Graph Partitioning Algorithms
SIAM Journal on Computing
Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A Scalable Hybrid Regular Expression Pattern Matcher
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A thesis on acceleration of network processing algorithms
A thesis on acceleration of network processing algorithms
Leaping multiple headers in a single bound: wire-speed parsing using the kangaroo system
INFOCOM'10 Proceedings of the 29th conference on Information communications
400 Gb/s Programmable Packet Parsing on a Single FPGA
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
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All network devices must parse packet headers to decide how packets should be processed. A 64 x 10Gb/s Ethernet switch must parse one billion packets per second to extract fields used in forwarding decisions. Although a necessary part of all switch hardware, very little has been written on parser design and the trade-offs between different designs. Is it better to design one fast parser, or several slow parsers? What is the cost of making the parser reconfigurable in the field? What design decisions most impact power and area? In this paper, we describe trade-offs in parser design, identify design principles for switch and router designers, and describe a parser generator that outputs synthesizable Verilog that is available for download. We show that i) packet parsers today occupy about 1-2% of the chip, and ii) while future packet parsers will need to be programmable, this only doubles the (already small) area needed.