Understanding sources of ineffciency in general-purpose chips
Communications of the ACM
Circuit design challenges at the 14nm technology node
Proceedings of the 48th Design Automation Conference
Compiling high throughput network processors
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Chisel: constructing hardware in a Scala embedded language
Proceedings of the 49th Annual Design Automation Conference
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation
Journal of Signal Processing Systems
Design principles for packet parsers
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
SWSL: software synthesis for network lookup
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
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Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethinking digital design. To reduce design costs, we need to stop building chip instances, and start making chip generators instead. Domain-specific chip generators are templates that codify designer knowledge and design trade-offs to create different application-optimized chips.