Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation

Authors:
Qiuling Zhu;Christian R. Berger;Eric L. Turner;Larry Pileggi;Franz Franchetti
Affiliations:
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA
Venue:
Journal of Signal Processing Systems
Year:
2013

Citing 11
Cited 0

An Interpolating Memory Unit for Function Evaluation: Analysis and Design

IEEE Transactions on Computers
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Digital Image Warping

Digital Image Warping
Combined DRAM and logic chip for massively parallel systems

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Pyramidal parametrics

SIGGRAPH '83 Proceedings of the 10th annual conference on Computer graphics and interactive techniques
Understanding Digital Signal Processing (2nd Edition)

Understanding Digital Signal Processing (2nd Edition)
Accelerating Compute-Intensive Applications with GPUs and FPGAs

SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Rethinking Digital Design: Why Design Must Change

IEEE Micro
An algorithm-architecture co-design framework for gridding reconstruction using FPGAs

Proceedings of the 48th Design Automation Conference
Measuring the Gap Between FPGAs and ASICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present a local interpolation-based variant of the well-known polar format algorithm used for synthetic aperture radar (SAR) image formation. We develop the algorithm to match the capabilities of the application-specific logic-in-memory processing paradigm, which off-loads lightweight computation directly into the SRAM and DRAM. Our proposed algorithm performs filtering, an image perspective transformation, and a local 2D interpolation, and supports partial and low-resolution reconstruction. We implement our customized SAR grid interpolation logic-in-memory hardware in advanced 14 nm silicon technology. Our high-level design tools allow to instantiate various optimized design choices to fit image processing and hardware needs of application designers. Our simulation results show that the logic-in-memory approach has the potential to enable substantial improvements in energy efficiency without sacrificing image quality.