The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HML, a novel hardware description language and its translation to VHDL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verischemelog: Verilog embedded in Scheme
Proceedings of the 2nd conference on Domain-specific languages
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Avoiding game over: bringing design to the next level
Proceedings of the 49th Annual Design Automation Conference
FPGA programming for the masses
Communications of the ACM
FPGA Programming for the Masses
Queue - Mobile Web Development
PHANTOM: practical oblivious computation in a secure processor
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
And then there were none: a stall-free real-time garbage collector for reconfigurable hardware
Communications of the ACM
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In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.