Transformation based communication and clock domain refinement for system design
Proceedings of the 39th annual Design Automation Conference
A case study of hardware and software synthesis in ForSyDe
Proceedings of the 15th international symposium on System Synthesis
A Higher-Level Language for Hardware Synthesis
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hardware Synthesis Using SAFL and Application to Processor Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Development and Application of Design Transformations in ForSyDe
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System Level Specification in Lava
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
EWD: A metamodeling driven customizable multi-MoC system modeling framework
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 13th ACM SIGPLAN international conference on Functional programming
A calculus for hardware description*
Journal of Functional Programming
Chisel: constructing hardware in a Scala embedded language
Proceedings of the 49th Annual Design Automation Conference
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We present hardware ML (HML), an innovative hardware description language (HDL) based on the functional programming language SML. Features of HML not found in other HDL's include polymorphic types and advanced type checking and type inference techniques. We have implemented an HML type checker and a translator for automatically generating VHDL from HML descriptions. We generate a synthesizable subset of VHDL and automatically infer types and interfaces. This paper gives an overview of HML and discusses the translation from HML to VHDL and the type inference process.