Semantics of digital circuits
How to make ad-hoc polymorphism less ad hoc
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Embedded real-time systems
Specification and design of embedded systems
Specification and design of embedded systems
Pizza into Java: translating theory into practice
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
OpenJ: an extensible system level design language
DATE '99 Proceedings of the conference on Design, automation and test in Europe
HML, a novel hardware description language and its translation to VHDL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the roles of functions and objects in system specification
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Designing systems-on-chip using cores
Proceedings of the 37th Annual Design Automation Conference
MASCOT: a specification and cosimulation method integrating data and control flow
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Transformation based communication and clock domain refinement for system design
Proceedings of the 39th annual Design Automation Conference
Object-Oriented Software Engineering: A Use Case Driven Approach
Object-Oriented Software Engineering: A Use Case Driven Approach
Structured Analysis and System Specification
Structured Analysis and System Specification
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Lava system provides novel techniques for representing system level specifications which are supported by a design flow that maps Lava descriptions onto System-on-Chip platforms implemented on very large FPGAs. The key contribution of this paper is a type class based approach for specifying bus-based system configurations. This provides a very flexible and parameterised flow for combining pre-designed IP blocks into a complete FPGA-based system.