High throughput architecture for packet classification using FPGA

Authors:
Zhang Tao;Wang Yonggang;Zhang Lijun;Yang Yang
Affiliations:
University of Science and Technology of China, Hefei, Anhui, P. R. China;University of Science and Technology of China, Hefei, Anhui, P. R. China;University of Science and Technology of China, Hefei, Anhui, P. R. China;University of Science and Technology of China, Hefei, Anhui, P. R. China
Venue:
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Year:
2009

Citing 1
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400 Gb/s Programmable Packet Parsing on a Single FPGA

Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems

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Abstract

To avoid packet classification from being the performance bottleneck in network devices, one-chip solution hardware packet classifier based on HiCuts algorithm is designed and implemented in single chip of FPGA. The compact data structure and the optimized combination of memory organization with high degree parallel and pipeline architecture make the classifier running at very high speed. The simulation and implementation tests show our design reaches OC-768 throughput even for a large rule set with 26K rules while only consuming limited logic resource of the FPGA. This low cost one-chip hardware solution can effectively off-load data processing burden from the CPU of data path in network devices.