An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Application-specific customization of soft processor microarchitecture
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A Multithreaded Soft Processor for SoPC Area Reduction
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Supporting multithreading in configurable soft processor cores
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A configurable multi-ported register file architecture for soft processor cores
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Making wide-issue VLIW processors viable on FPGAs
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Multi-ported memories for FPGAs via XOR
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Versatile design of shared vector coprocessors for multicores
Microprocessors & Microsystems
Securing multi-core multi-threaded packet processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Bitmask aware compression of NISC control words
Integration, the VLSI Journal
An out-of-order superscalar processor on FPGA: the ReOrder buffer design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Multicore-based vector coprocessor sharing for performance and energy gains
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Scalable ternary content addressable memory implementation using FPGAs
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
Modular multi-ported SRAM-based memories
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of FPGA-based soft multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implementation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2x smaller.