A configurable multi-ported register file architecture for soft processor cores

Authors:
Mazen A. R. Saghir;Rawan Naous
Affiliations:
Department of Electrical and Computer Engineering, American University of Beirut, Lebanon;Department of Electrical and Computer Engineering, American University of Beirut, Lebanon
Venue:
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Year:
2007

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Abstract

This paper describes the architecture of a configurable, multi-ported register file for soft processor cores. The register file is designed using the low-latency block RAMs found in high-density FPGAs like the Xilinx Virtex-4. The latency of the register file and its utilization of FPGA resources are evaluated with respect to design parameters that include word length, register file size, and number of read and write ports. Experimental results demonstrate the flexibility, performance, and area efficiency of our proposed register file architecture.