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IEEE Transactions on Computers
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Interlock collapsing ALU for increased instruction-level parallelism
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The optimum pipeline depth for a microprocessor
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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
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Increasing processor performance by implementing deeper pipelines
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High-Performance 3-1 Interlock Collapsing ALU's
IEEE Transactions on Computers
A high performance 32-bit ALU for programmable logic
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Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
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Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates. We then use the results of these comparisons to infer how the microarchitecture of soft processors on FPGAs should be different from hard processors on custom CMOS. We find that the ratios of the area required by an FPGA to that of custom CMOS for different building blocks varies significantly more than the speed ratios. As area is often a key design constraint in FPGA circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores have area ratios of 17-27x and delay ratios of 18-26x. Building blocks that have dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7x area ratio), while multiplexers and CAMs are particularly area-inefficient (100x area ratio), leading to cheaper ALUs, larger caches of low associativity, and more expensive bypass networks than on similar hard processors. We also find that a low delay ratio for pipeline latches (12-19x) suggests soft processors should have pipeline depths 20% greater than hard processors of similar complexity.