Identification of critical paths in circuits with level-sensitive latches
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A timing analysis algorithm for circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
FPGA prototyping of a RISC processor core for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Micro
A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
Static statistical timing analysis for latch-based pipeline designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An FPGA-based Pentium® in a complete desktop system
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
FPGA prototyping of an amba-based windows-compatible SoC
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Mixing static and dynamic strategies for high performance and low area reconfigurable systems
International Journal of High Performance Systems Architecture
Resource-bounded multicore emulation using Beefarm
Microprocessors & Microsystems
An out-of-order superscalar processor on FPGA: the ReOrder buffer design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads.