MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
Transparent reconfigurable acceleration for heterogeneous embedded applications
Proceedings of the conference on Design, automation and test in Europe
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Limits of parallelism using dynamic dependency graphs
WODA '09 Proceedings of the Seventh International Workshop on Dynamic Analysis
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Reconfigurable architectures can be seen as a possible solution to increase performance of current embedded systems. While dynamic reconfigurable systems present different degrees of adaptability at the price of huge area overhead, static exploitation tools can be used at design time to generate a tailored reconfigurable unit with small area requirements. However, the speedup using static tools will be limited only to the specific application set previously analysed. Therefore, we propose a technique that presents the best compromise between both approaches. After a high performance and low-power reconfigurable unit, optimised in area, is produced by a static exploitation tool, it is coupled to a dynamic hardware mechanism responsible for accelerating applications not foreseen at design time. Hence, both the capability of adaptation and the binary compatibility are maintained. We are able to save up to 40% in area and 77% in power, without significant losses in performance or adaptability.