Efficient multi-ported memories for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Design of a secure packet processor
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Inferring Packet Processing Behavior Using Input/Output Monitors
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
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Modern routers use high-performance multi-core multi-threaded packet processing systems to implement protocol operations and to forward traffic. As the number of processor cores/threads increases, it becomes increasingly difficult to track their correct operation at runtime. In this paper, we discuss how to extent our existing monitoring scheme to support highly parallel environments.