Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Utilizing Formal Assertions for System Design of Network Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low power network processor design using clock gating
Proceedings of the 42nd annual Design Automation Conference
NPCryptBench: a cryptographic benchmark suite for network processors
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
Efficient memory utilization on network processors for deep packet inspection
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
High-throughput sketch update on a low-power stream processor
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Conserving network processor power consumption by exploiting traffic variability
ACM Transactions on Architecture and Code Optimization (TACO)
SimNP: a flexible platform for the simulation of a network processing system
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Low power architecture for high speed packet classification
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Analysis of network processing workloads
Journal of Systems Architecture: the EUROMICRO Journal
Compiler assisted dynamic management of registers for network processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Enhancing network processor simulation speed with statistical input sampling
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Exploiting a computation reuse cache to reduce energy in network processors
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Efficient traffic aware power management in multicore communications processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
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This open-source integrated simulation infrastructure contains a cycle-accurate simulator for a typical network processor architecture, an automatic verification framework for testing and validation, and a power estimation model for measuring the simulated processor's power consumption.