i860 microprocessor family programmer's reference manual
i860 microprocessor family programmer's reference manual
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Case for Clumsy Packet Processors
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Optimizing throughput and latency under given power budget for network packet processing
INFOCOM'10 Proceedings of the 29th conference on Information communications
Clock network synthesis with concurrent gate insertion
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Exploiting a computation reuse cache to reduce energy in network processors
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient traffic aware power management in multicore communications processors
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multi-threading to achieve maximum parallel processing capabilities. We observed that under low incoming traffic rates, most processing elements (PEs) in NPs are nearly idle and yet still consume dynamic power. This paper develops a low power technique to reduce the activities of PEs according to the varying traffic volume. We propose to monitor the average number of idle threads in a time window, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. We show that our technique brings significant reduction in power consumption (up to 30%) of NPs with no packet loss and little impact to the overall throughput.