Exploiting a computation reuse cache to reduce energy in network processors

Authors:
Bengu Li;Ganesh Venkatesh;Brad Calder;Rajiv Gupta
Affiliations:
CS Dept., University of Arizona, Tucson, AZ;CSE Dept., University of California, San Diego, La Jolla, CA;CSE Dept., University of California, San Diego, La Jolla, CA;CS Dept., University of Arizona, Tucson, AZ
Venue:
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Year:
2005

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Abstract

High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a traditional processor, and provide no additional throughput for a balanced network processor design. This is why most high end routers do not use caches for their data plane algorithms. In this paper we examine how to use a cache for a balanced high bandwidth network processor. We focus on using a cache not as a latency saving mechanism, but as an energy saving device. We propose using a Computation Reuse Cache that caches the answer to a query for data-plane algorithms, where the tags are the inputs to the query and the block the result of the query. This allows the data-plane algorithm to perform a complete query in one cache access if there is a hit. This creates slack by reducing the number of instructions executed. We then exploit this slack by fetch-gating the data-plane algorithm while matching the worst case throughput guarantees of the rest of the network processor. We evaluate the computation reuse cache for network data-plane algorithms IP-lookup, Packet Classification and NAT protocol.