Proceedings of the 24th annual international symposium on Computer architecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Understanding the differences between value prediction and instruction reuse
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Compiler-directed dynamic computation reuse: rationale and initial results
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Unification-based pointer analysis with directional assignments
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Hardware support for dynamic activation of compiler-directed computation reuse
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Interprocedural Def-Use Associations for C Systems with Single Level Pointers
IEEE Transactions on Software Engineering
Exploiting Basic Block Value Locality with Block Reuse
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
SoftSig: software-exposed hardware signatures for code analysis and optimization
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Partial resolution for redundant operation table
Microprocessors & Microsystems
Fast Track: A Software System for Speculative Program Optimization
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Exploiting a computation reuse cache to reduce energy in network processors
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
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Recent research has shown that programs often exhibitvalue locality. Such locality occurs when a code segment,although executed repeatedly in the program, takes only asmall number of different values as input and, naturally,generates a small number of different outputs. It is potentiallybeneficial to replace such a code segment by a tablewhich records the computation results for the previous inputs.When the program execution re-enters the code segmentwith a repeated input, its computation can be simplifiedto a table look-up. In this paper, we discuss a compilerscheme to identify code segments which are good candidatesfor computation reuse. We discuss the conditions underwhich the table look-up costs less than repeating theexecution, and we perform profiling to identify candidateswhich have many repeated inputs at run time. Comparedto previous work, this scheme requires no special hardwaresupport and is therefore particularly useful for resourceconstrained systems such as handheld computing devices.We implement our scheme and its supporting analysesin GCC. We experiment with several multimedia benchmarksand the GNU Go game by executing them on a handheldcomputing device. The results show the scheme to improvethe performance and to reduce the energy consumptionquite substantially for these programs.