Instruction flow-based front-end throttling for power-aware high-performance processors

Saving energy with just in time instruction delivery

Proceedings of the 2002 international symposium on Low power electronics and design

Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors

IEEE Design & Test

Adapting instruction level parallelism for optimizing leakage in VLIW architectures

Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems

Power-Aware Control Speculation through Selective Throttling

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture

Front-End Policies for Improved Issue Efficiency in SMT Processors

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture

Energy efficient co-adaptive instruction fetch and issue

Proceedings of the 30th annual international symposium on Computer architecture

Combining compiler and runtime IPC predictions to reduce energy in next generation architectures

Proceedings of the 1st conference on Computing frontiers

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

Proceedings of the 31st annual international symposium on Computer architecture

Power-performance trade-off using pipeline delays

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption

IEEE Micro

Control Speculation for Energy-Efficient Next-Generation Superscalar Processors

IEEE Transactions on Computers

Power-efficient instruction delivery through trace reuse

Proceedings of the 15th international conference on Parallel architectures and compilation techniques

Stall cycle redistribution in a transparent fetch pipeline

Proceedings of the 2006 international symposium on Low power electronics and design

Addressing instruction fetch bottlenecks by using an instruction register file

Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

Fetch Gating Control through Speculative Instruction Window Weighting

Transactions on High-Performance Embedded Architectures and Compilers II

Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

Fetch gating control through speculative instruction window weighting

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers

Early-stage definition of LPX: a low power issue-execute processor

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems

Dynamic tag-check omission: a low power instruction cache architecture exploiting execution footprints

PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems

Exploiting a computation reuse cache to reduce energy in network processors

HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers